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Auf einen Rechner - ein informationsverarbeitendes System aus Hardware und Software - sollte Verlass sein. Das ist eine Anforderung, die in der Praxis oft nur mit sehr großem Aufwand oder in unbefriedigendem Maße zu erfüllen ist. Das Buch vermittelt einen umfassenden Überblick über die Probleme und Maßnahmen, mit denen die Verlässlichkeit informationsverarbeitender Systeme gesichert wird. Großer Wert wurde auf abschätzbare Kenngrößen und anschauliche Experimente für ihre Abschätzung gelegt. Quantitativ gesehen sind die kritschen Teile in der gesamten Maßnahmenkette die Tests und Überwachungsfunktionen, die die Fehler und Fehlfunktionen in den Systemen offenlegen, bevor darauf reagiert werden kann. Die Antwort auf das Problem, dass die Systeme immer größer werden und immer umfangreichere Tests erfordern, ist der Selbsttest. Das Buch richtet sich an Studierende der Fachrichtungen Informatik und Informationstechnik in höheren Semestern. Praktiker aus den Bereichen Entwicklung, Test und Qualitätssicherung werden in dem Buch zahlreiche interessante Anregungen finden.

Computer hardware. --- Computer Hardware.

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Forum on specification & Design Languages (FDL) is a well established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modelling and verification of integrated circuits, complex hardware software embedded systems, and mixed technology systems Modelling and specification concepts push the development of new design and verification methodologies to ESL (Electronic System Level) thus providing a means for model driven and automated design of complex electronic systems in a variety of application domains FDL gives an opportunity to gain up to date knowledge in many broad areas of the fast evolving field of system design and verification Through collaboration with the Accellera Systems Initiative FDL maintains a strong link to many EDA standards like SystemC, OCP and IP XACT.

Computer hardware description languages

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The Core Test Language (CTL) is a language created for a System-on-Chip flow (or SoC flow), where a design created by one group is reused as a sub-design of a design created by another group. In an SoC flow, the smaller design embedded in the larger design is commonly called a core and the larger design is commonly called the SoC. The core is a design provided by a core provider, and the task of incorporating the sub-design into the SoC is called Core System Integration.

Computer hardware description languages.

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The IEEE Property Specification Language (PSL) is defined in this standard. PSL is a formal notation for specification of electronic system behavior, compatible with multiple electronic system design languages, including IEEE Std 1076™ (VHDL®), IEEE Std 1354 (Verilog®), IEEE Std 1666™ (SystemC®), and IEEE Std 1800(TM) (SystemVerilog(R)), thereby enabling a common specification and verification flow for multi-language and mixed-language designs. PSL captures design intent in a form suitable for simulation, formal verification, formal analysis, and hybrid verification tools. PSL enhances communication among architects, designers, and verification engineers to increase productivity throughout the design and verification process. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.

Computer hardware description languages.

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Computer hardware description languages