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IEEE Std 896.1-1991 provides a set of tools with which to implement a Futurebus+architecture with performance and cost scalability over time, for multiple generations of single- and multiple-bus multiprocessor systems. Although this specification is principally intended for 64-bit address and data operation, a fully compatible 32-bit subset is provided, along with compatible extensions to support 128- and 256-bit data highways. Allocation of bus bandwidth to competing modules is provided by either a fast centralized arbiter, or a fully distributed, one or two pass, parallel contention arbiter. Bus allocation rules are provided to suit the needs of both real-time (priority based) and fairness (equal opportunity access based) configurations. Transmission of data over the multiplexed address/data highway is governed by one of two intercompatible transmission methods: (1) a technology-independent, compelled-protocol, supporting broadcast, broadcall, and transfer intervention (the minimum requirement for all Futurebus+systems), and (2) a configurable transfer-rate, source-synchronized protocol supporting only block transfers and source-synchronized broadcast for systems requiring the highest possible performance.
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The IEEE 959 I/O expansion bus concept allows low-cost, highly flexible I/O expansion for computer boards. The specification describes the elements of the bus system, the bus interface signals, and the bus operations. The electrical considerations required for the bus include the following: logical and electrical state relationships, environmental considerations, power supply specifications, signal line characteristics, timing specifications, and driver/receiver specifications. The specification describes the physical and mechanical specifications that a designer must be concerned with when designing a baseboard or an expansion module compatible with the IEEE 959 I/O expansion bus. It specifies the requirements of a miniature two-piece stacking connector to be used in both the 8- and 16-bit versions of the IEEE 959 I/O expansion bus. Finally, it presents the concept and notation of levels of compliance.
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The International Workshop on Advances in Sensors and Interfaces is a premier Sensors and Interface design Worksho paimed at bridging the gap between electronic design and integrated circuit technologies, processes, and manufacturing to achieve design quality in sensors developments and in electronic interfaces The conference provides a network to present and exchange ideas, promoting research, development, and applications in a wide range of sensor and interface fields Spans biomedical, chemical, high energy physics and space automotive sensors to their interfaces in harsh and heterogeneous environments and sensor networks.
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A high-bandwidth interface optimized for interchanging data between a memory controller and one or more dynamic RAMs is specified. RamLink is an applicable interface for other RAM-like devices as well.
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Annotation Provides the Managed Object Conformance Statement (MOCS) proforma as a supplement to IEEE Std 802.9 Integrated Services Local Area Network (ISLAN) Interface at the Medium Access Control (MAC) Sublayer and Physical Layer.
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