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Book
Implementing functional languages : [a tutorial]
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ISBN: 0137219520 9780137219520 Year: 1992 Publisher: New York, NY : Prentice-Hall,

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Formal specification of programming languages : a panoramic primer
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ISBN: 0133290522 Year: 1981 Publisher: Englewood Cliffs, NJ : Prentice-Hall,

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Book
Programming language concepts 2/E : 2/E
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ISBN: 0471853992 9780471853992 Year: 1987 Publisher: New York, NY : John Wiley,

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Book
IEEE Std 1364-2005 : IEEE Standard for Verilog Hardware Description Language
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ISBN: 0738148504 0738148512 Year: 2006 Publisher: New York, USA : IEEE,

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The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language. (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).


Book
2013 IEEE Symposium on Adaptive Dynamic Programming and Reinforcement Learning (ADPRL)
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ISBN: 1467359254 1467359246 Year: 2013 Publisher: Piscataway, New Jersey : IEEE,

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Adaptive (or Approximate) dynamic programming (ADP) is a general and effective approach for solving optimal control problems by adapting to uncertain environments over time ADP optimizes a user defined cost function with respect to an adaptive control law, conditioned on prior knowledge of the system, and its state, in the presence of system uncertainties A numerical search over the present value of the control minimizes a nonlinear cost function forward in time providing a basis for real time, approximate optimal control The ability to improve performance over time subject to new or unexplored objectives or dynamics has made ADP an attractive approach in a number of application domains including optimal control and estimation, operation research, and computational intelligence ADP is viewed as a form of reinforcement learning based on an actor critic architecture that optimizes a user prescribed value online and obtains the resulting optimal control policy.


Book
IEEE Standard for the Scheme Programming Language
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ISBN: 0738111899 0738111880 1665419644 Year: 2020 Publisher: Piscataway, NJ : IEEE,

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Book
IEEE Std 1364-1995 : IEEE Standard Hardware Description Language Based on the Verilog(R) Hardware Description Language
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ISBN: 0738130656 Year: 1996 Publisher: New York, New York : IEEE,

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The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.


Book
IEEE Std 1647-2011 (Revision of IEEE Std 1647-2008) : IEEE standard for the functional verification language e
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ISBN: 0738166871 Year: 2011 Publisher: Piscataway, New Jersey : IEEE,

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The e functional verification language is an application-specific programming language, aimed at automating the task of verifying a hardware or software design with respect to its specification. Verification environments written in e provide a model of the environment in which the design is expected to function, including the kinds of erroneous conditions the design needs to withstand. A typical verification environment is capable of generating user-controlled test inputs with statistically interesting characteristics. Such an environment can check the validity of the design responses. Functional coverage metrics are used to control the verification effort and gauge the quality of the design, e verification environments can be used throughout the design cycle, from a high-level architectural model to a fully realized system. A definition of the e language syntax and semantics and how tool developers and verification engineers should use them are contained in this standard.


Book
IEEE Std 1647-2011 (Revision of IEEE Std 1647-2008) - Redline : IEEE standard for the functional verification language e - Redline
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ISBN: 073818019X Year: 2011 Publisher: New York, New York : IEEE,

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The e functional verification language is an application-specific programming language, aimed at automating the task of verifying a hardware or software design with respect to its specification. Verification environments written in e provide a model of the environment in which the design is expected to function, including the kinds of erroneous conditions the design needs to withstand. A typical verification environment is capable of generating user-controlled test inputs with statistically interesting characteristics. Such an environment can check the validity of the design responses. Functional coverage metrics are used to control the verification effort and gauge the quality of the design. e verification environments can be used throughout the design cycle, from a high-level architectural model to a fully realized system. A definition of the e language syntax and semantics and how tool developers and verification engineers should use them are contained in this standard.


Book
ISO/IEC/IEEE 31320-1:2012 (Adoption of IEEE Std 1320.1-1998). : Information technology -- Modeling Languages
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ISBN: 0738180017 Year: 2012 Publisher: Geneva, New York : IEEE,

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IDEF0 function modeling is designed to represent the decisions, actions, and activities of an existing or prospective organization or system. IDEF0 graphics and accom-panying texts are presented in an organized and systematic way to gain understanding, support analysis, provide logic for potential changes, specify requirements, and support system-level design and integration activities. IDEF0 may be used to model a wide variety of systems, composed of people, machines, materials, computers, and information of all varieties and structured by the relationships among them, both automated and nonautomated. For new systems, IDEF0 may be used first to define requirements and to specify functions to be carried out by the future system. As the basis of this architecture, IDEF0 may then be used to design an implementation that meets these requirements and performs these functions. For existing systems, IDEF0 can be used to analyze the functions that the system performs and to record the means by which these are done. Keywords: enterprise, functional modeling language, IDEF0, language, modeling language.

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