TY - BOOK ID - 5455442 TI - Skew-tolerant circuit design PY - 2001 SN - 155860636X 9786611078041 1281078042 0080541267 9780080541266 9781558606364 9781281078049 6611078045 PB - San Francisco : Morgan Kaufmann Publishers, DB - UniCat KW - Timing circuits KW - Integrated circuits KW - Synchronization. KW - Minuteries KW - Circuits intégrés à très grande échelle KW - Synchronisation KW - Design and construction. KW - Very large scale integration KW - Design and construction KW - Conception et construction KW - Synchronization KW - Circuits d'horloge KW - Circuits intégrés à très grande échelle KW - Synchronisation. KW - Conception et construction. KW - Synchronism KW - Time measurements KW - Electronic circuits UR - https://www.unicat.be/uniCat?func=search&query=sysid:5455442 AB - As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, th ER -