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The papers in this volume were presented at an ACM Symposium on Principals of Programming Languages, sponsored jointly by SIGACT and SIGPLAN. These papers were selected from over 100 abstracts submitted in response to the Committee's call for papers. The Committee wishes to thank all those who submitted abstracts for consideration.The papers in these Proceedings have not been formally refereed, and several of the papers represent preliminary reports of ongoing research. It is anticipated that most of these papers will appear in more complete form in scientific journals.
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The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language. (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).
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The Verilog Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.
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