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As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, th

Timing circuits --- Integrated circuits --- Synchronization. --- Minuteries --- Circuits intégrés à très grande échelle --- Synchronisation --- Design and construction. --- Very large scale integration --- Design and construction --- Conception et construction --- Synchronization --- Circuits d'horloge --- Circuits intégrés à très grande échelle --- Synchronisation. --- Conception et construction. --- Synchronism --- Time measurements --- Electronic circuits